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OX16PCI958 DATA SHEET Octal UART with PCI Interface
FEATURES
* Efficient 32-bit, 331/3 MHz multi-function, target-only PCI controller, compliant to PCI Local Bus Specification 3.0 & PCI Power Management Specification 1.1 Eight UARTs fully software compatible with 16C550type devices Compatible with existing 16C550/450 device drivers PCI 2.1, 2.2, 2.3 & 3.0 compliant Supports both 5.0-V & 3.3-V PCI signalling 32-byte deep FIFO per transmitter & receiver Baud rates up to 4.125 Mega-baud (using a 16.5 MHz input clock). Clock can be provided from crystal oscillator or external clock source Automated out-of-band flow control using CTS#/RTS# Configuration data is held in a small, low-cost serial MicrowireTM compatible EEPROM * * * * Driver-facilitated DSR/DTR & Xon/Xoff handshaking 5-,6-,7- & 8-bit data framing 1, 1.5 or 2 stop bits UART enhancements: * Clock prescaler allows more baud rate options * Readable FIFO levels & tuneable trigger levels improve device driver performance * Programmable "synchronization factor" allows baud rates up to fclock/4 * Extensions to standard register set are implemented in a safe, easy-to-use way Low-power design with separate power management control Operating temp. range : 0oC--70oC 160-pin QFP package Operation via IO or memory mapping Support for multiple wake-up events
* * * * * * * * *
* * * * *
DESCRIPTION
The OX16PCI958 contains eight UARTs (Universal Asynchronous Receiver-Transmitters) and a host interface suitable for direct connection to a PCI bus. Once installed and configured by the host OS, it provides an eight-byte programming interface to each UART. The UARTs are fully software-compatible with 16C550 devices. The device can be configured to fit the requirements of RS232 or RS422 applications. The UARTs convert between RS232-format serial data on separate transmit and receive lines, and byte-wide I/O writes and reads on the host interface. Malformed incoming serial data is flagged along with the data in the receive FIFO. The state of the UART can be found at any time by reading status registers, and modem control (handshaking output) lines can be individually controlled. Although polled-mode operation is possible, the UART will usually be operated on a host-interrupt basis. The interrupt system is designed to allow efficient handling of interrupt service requests from the UART, for example by using the prioritised interrupt identification register, readable FIFO levels, and tuneable FIFO trigger levels. The internal transmitter and receiver logic runs at a programmable synchronisation factor of 4x, 8x, or 16x the serial baud rate. This internal clock is generated by dividing a reference clock by an integer divisor from 1 to (216-1). In this way the UART can accommodate a serial rate of up to 4 125 000 baud (using a 16.5 MHz input clock). The OX16PCI958 provides a host interface that can be directly connected to a PCI bus. It responds to configuration accesses, and once configured it also responds to I/O and memory accesses for control of the UART. The data for configuration space is read from a small external serial EEPROM at start-up, together with information on how the OX16PCI958 should be set up.
Oxford Semiconductor Ltd. 25 Milton Park, Abingdon, Oxon, OX14 4SH, UK Tel: +44 (0)1235 824900
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Oxford Semiconductor 2005 OX16PCI958 DS-0022--Nov 2005 Part No. OX16PCI958--PQAG
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OX16PCI958 DATA SHEET
CONTENTS
Features Description Contents 1. Block Diagram 2. Pin Information--160-pin QFP 2.1. Pinout 2.2. Pin Descriptions 3. PCI interface 3.1. Internal Address Map 3.2. Configuration & Control Registers 3.3. PCI Configuration Space Registers 3.4. PCI Set-up Registers 4. UART function 4.1. Programming 4.2. Accessible Registers 4.3. Serial Data Format 4.4. Transmitter/Receiver Section 4.5. FIFO Interrupt Mode Operation 4.6. FIFO Polled Mode Operation 4.7. Loopback Mode 4.8. Auto Flow Control 4.8.1. Auto-RTS 4.8.2. Auto-CTS 4.8.3. Enabling Auto-RTS & Auto-CTS 4.9. Chip Type Identification 4.10. SISR Function 5. EEPROM 5.1. The EEPROM Reader 5.2. EEPROM Data Format 5.3. Example EEPROM Data 6. Clock/Oscillator Pins 7. Operating conditions 7.1. Recommended Operating Conditions 7.2. DC Characteristics 8. I/O electrical & timing specifications 9. Package information 10. Glossary 11. Ordering information 12. Contact Details 1 1 2 3 4 4 5 7 7 9 11 15 16 16 16 21 21 24 25 26 27 28 28 28 29 30 31 31 32 33 35 36 36 36 37 43 44 45 46
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OX16PCI958 DATA SHEET
1. BLOCK DIAGRAM
PCI Bus
PCI Interface
EEPROM Signals
32-bit - 8-bit Bridge
Address Encode
EEPROM Reader
Arbiter
PCI Side Configuration Registers PCI Clock Domain Local Clock Domain
Asynchronous Bridge
Address Decode
Local Side Configuration Registers
UART
UART
UART
UART
UART
UART
UART
UART
UART RAM Blocks
I/O Switching
I/O Banks
Note: The connections between the UART RAM blocks and each of the UARTs are omitted for clarity.
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2. PIN INFORMATION--160-PIN QFP
2.1. Pinout
VDD DCD2 RI1 DTR1 CTS1 VSS SOUT1 RTS1 SIN1 VDD DSR1 DCD1 RI0 DTR1 VSS CTS0 SOUT0 RTS0 VDD SIN0 DSR0 DCD0 DCD4 VSS DSR4 SIN4 RTS4 VDD SOUT4 CTS4 DTR4 RI4 VSS DCD5 DSR5 SIN5 VDD RTS5 SOUT5 NC
DSR2 SIN2 RTS2 VSS SOUT2 CTS2 DTR2 RI2 VDD DCD3 DSR3 SIN3 RTS3 VSS SOUT33 CTS3 DTR3 VDD RI3 LINEDRIVER_EN VDD VSS INTA# RST# CLK PME# VDDP AD31 AD30 AD29 VSS AD28 AD27 AD26 AD25 VDDP AD24 VSS C/BE#3 IDSEL
121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
OX16PCI958
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
CTS5 XTALO XTALI VSS DTR5 RI5 VDD DCD6 DSR6 SIN6 RTS6 VSS SOUT6 CTS6 DTR6 VDD RI6 DCD7 DSR7 SIN7 VSS RTS7 SOUT7 CTS7 VDD DTR7 RI7 EECS EECK VSS EEDIO MODE0 TESTN VDDP VDD AD0 AD1 AD2 VSS AD3
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AD23 VDDP AD22 AD21 AD20 VSS AD19 AD18 AD17 AD16 VDDP C/BE#2 FRAME# IRDY# VSS TRDY# DEVSEL# STOP# PERR# VDDP SERR# PAR C/BE#1 VSS AD15 AD14 AD13 AD12 VDDP AD11 AD10 AD9 VSS AD8 C/BE#0 AD7 AD6 VDDP AD5 AD4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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2.2.
Pin Descriptions
Table 1 lists the pin allocations, names and describes them. Table 1 Pin Descriptions Name
PAR CLK RST# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# INTA# PME# IDSEL AD[31:0] C/BE#3 C/BE#2 C/BE#1 C/BE#0 EECS EECK EEDIO XTALI XTALO LD_EN VSS (GND) VDD (5V) VDDP 22 145 144 13 14 16 17 18 19 21 143 146 160
Pin
IO I I I I OT OT OT OT OT OT OT I
Dir
Description
PCI bus signals
148, 149,150, 152, 153, 154, 155, 157, 1, 3, 4, 5, 7, 8, 9, 10, 25, 26, 27, 28, 30, 31, 32, 34, 36, 37, 39, 40, 41, 43, 44, 45 IO 159 12 23 35 53 52 50 78 79 140 I I I I Chip configuration O O IO Local clock I O Local side O Power and ground 6, 15, 24, 33, 42, 49, 51, 60, 69, 77, 88, 97, 106, 115, 124, 134, 142, 151, 158 56, 65, 74, 84, 93, 102, 111, 120, 129, 138 2, 11, 20, 29, 38, 46, 47, 141, 147, 156
The VDDP pins provide power to the PCI I/O buffers, and must be connected to the +VI/O pins on the PCI connector. Table 2 &
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Table 3 list pin allocations for the local I/O banks. Table 2 Local I/O Bank 0--3 Pin Allocations
IO# 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Bank 0 Pin 99 100 101 103 104 105 107 108 109 110 112 113 114 116 117 118 119 121 122 123 125 126 127 128 130 131 132 133 135 136 137 139 Dir I I I O O I O I I I I O O I O I I I I O O I O I I I I O O I O I Name DCD DSR SIN RTS SOUT CTS DTR RI DCD DSR SIN RTS SOUT CTS DTR RI DCD DSR SIN RTS SOUT CTS DTR RI DCD DSR SIN RTS SOUT CTS DTR RI
OX16PCI958 DATA SHEET
Table 3 Local I/O Bank 4--7 Pin Allocations
IO# 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Bank 4 Pin 98 96 95 94 92 91 90 89 87 86 85 83 82 80 76 75 73 72 71 70 68 67 66 64 63 62 61 59 58 57 55 54 Dir I I I O O I O I I I I O O I O I I I I O O I O I I I I O O I O I Name DCD DSR SIN RTS SOUT CTS DTR RI DCD DSR SIN RTS SOUT CTS DTR RI DCD DSR SIN RTS SOUT CTS DTR RI DCD DSR SIN RTS SOUT CTS DTR RI
1
5
2
6
3
7
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3. PCI INTERFACE
The PCI interface conforms to revisions 2.1, 2.2, 2.3 and 3.0 of the PCI Specification, and version 1.1 of the PCI Power Management Specification. Six base address registers are implemented in the OXPCI958: * * * * * * BAR0--128-byte memory-mapped region BAR1--128-byte I/O-mapped region BAR2--64-byte I/O-mapped region BAR3--16-byte I/O-mapped region BAR4--64-byte memory-mapped region BAR5--16-byte memory-mapped region
All memory regions are in 32-bit address space, and are marked as non-prefetchable.
3.1.
Internal Address Map
The internal address map is referenced by the EEPROM to configure the UARTs. Table 4 shows how PCI accesses are mapped to internal addresses: Table 4 PCI Address Mapping
PCI side BAR0, 1 local side configuration local functions local functions PCI bridge configuration EEPROM control, power management UART, SISR UARTs SISR 00h to 2Fh 30h to 3Fh 40h to 7Fh 80h to BFh C0h to CFh
BAR2, 4 BAR3, 5
Notes: * * Addresses in the range 40h-7Fh are aliased with a period of 32, i.e., address bit 5 is not decoded in this range Addresses in the range C0h-FFh are aliased with a period of 16, i.e., address bits 5:4 are not decoded in this range. For example, if BAR4 is configured as C8000400h, a memory access at C8000413h, which is BAR4+13h, would access internal address 80h+13h = 93h The serial EEPROM reader can access any internal address
*
Table 5 lists the PCI register offsets.
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Table 5 Register Offsets
BAR BAR0, 1 Internal address 00h - 19h 30h 31h 34h 35h 40h 41h 42h 4Ch 50h BAR2,4 80h-87h 88h-8Fh 90h-97h 98h-9Fh A0h-A7h A8h-AFh B0h-B7h B8h-BFh BAR3,5 C0h C0h-C1h C2h-C3h C4h-C5h C6h-C7h C8h-C9h CAh-CBh CCh-CDh CEh-CFh other UART-enable register UART IO bank switching/rotation SISR enable register UART configuration Global UART clock pre-divider UART 0 registers 0-7 UART 1 registers 0-7 UART 2 registers 0-7 UART 3 registers 0-7 UART 4 registers 0-7 UART 5 registers 0-7 UART 6 registers 0-7 UART 7 registers 0-7 SISR, if SISR enabled UART 0 registers 8-9, if SISR not enabled UART 1 registers 8-9 UART 2 registers 8-9 UART 3 registers 8-9 UART 4 registers 8-9 UART 5 registers 8-9 UART 6 registers 8-9 UART 7 registers 8-9 RFU Use PCI setup registers, as described in section 3.4. EEPROM-control register Power-management control register UART interrupt status
Notes: * * Writes to undefined internal addresses are ignored, and reads from undefined internal addresses return zero For shared address ranges, the SISR takes priority over the UARTs
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3.2.
Configuration & Control Registers
Table 6 summarizes the configuration and control registers for quick reference. Table 6 Configuration & Control Register Summary
A 30h use EEPROMcontrol register Powermanagement control register UART interrupt status (RO) UART-enable register SISR enable UART configuration Global predivider RFU1 D7 EET2 D6 EET1 D5 RFU D4 EEDIO data in D3 EECS D2 EECK D1 EEDIO output enable PM_OSC U2INT U2EN U1INT U1EN U0INT U0EN D0 EEDIO data out
31h 34h 40h 42h 4Ch 50h
RFU U7INT U7EN SEN RFU RFU1 U6INT U6EN
PM_DRIVER U5INT U5EN U4INT U4EN
PM_LCLK U3INT U3EN RFU
1b GCS1 RFU1 RFU
RFU GCS0 RFU1 RFU
EEPROM-Control Register
The OX16PCI958 automatically takes control of the EECS, EECK and EEDIO pins after a deassertion of the host bus RESET signal, in order to read in configuration data. Afterwards, the signals may be controlled though accesses to this register.
Field (Bits) EET2 (7) Description High--at least 70 PCI clock cycles have occurred since the register was last written. Cleared when the register is written. Set to the value of EET1 every 70th PCI clock cycle. This may be useful for ensuring that EEPROM timing constraints are met Cleared when the register is written. Set every 70th PCI clock cycle Returns the current logic level on the EEDIO pin. Controls EECS output. Controls EECK output 1--the value last written to bit 0 is driven on the EEDIO pin 0--EEDIO pin is tri-stated Controls the logic level driven onto EEDIO when bit 1 is set.
EET1 (6) EEDIO data in (4) EECS (3) EECK (2) EEDIO output enable (1) EEDIO data out (0)
This register is set to 00h on a PCI reset.
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Power-Management Control Register
Each two-bit group represents a powermanagement level range, as shown in Table 7, defining whether an element is disabled, which is shown in Table 8. Table 7 Power Management Group
Field (Bits) PM_DRIVER PM_LCLK PM_OSC Control Measure driver_en output deasserted Local-side clock gated off Local-side oscillator disabled
Global UART Clock Pre-Divider
This register sets a pre-division value for all the internal UARTs. Bit 5--One of the clock pre-division factors, see Table 9 Bit 2--One of the clock pre-division factors, see Table 9 After a reset, this register is set to F6h, giving a divide-by-8 clock setting for all UARTs. For the standard 14.7456 MHz external crystal, this gives a 1.8432 MHz effective clock to the UARTs. For backwards compatibility, write only one of the four values in Table 9 to bits 5 and 2: Table 9 Clock Pre-Division Values
Value F6h F2h D6h D2h Divisor 8 4 2 1
Table 8 Element Disabling
Value 00 01 10 11 Description Never disabled Disabled in D1, D2 & D3 Disabled in D2 and D3 Disabled in D3 only
This register is set to 00h on a PCI reset.
UART Interrupt State
Each bit in this read-only register reports the interrupt status of the corresponding internal UART.
The above register settings are recommended for backwards compatibility, but Table 10 shows how the actual control logic operates. Table 10 Clock Division Logic
GCS1 1 1 0 0 GCS0 1 0 1 0 Division 8 4 2 1
UART Enable
Each bit in this register enables the corresponding internal UART to be accessed on the internal bus, by either the PCI interface or the EEPROM reader.
SISR Enable
Bit 7 must be set to enable access to the shared interrupt status register (SISR). This register is set to 80h on a PCI reset.
UART Configuration
Bit 5 must be set to binary 1 to ensure correct operation of the UART
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3.3.
PCI Configuration Space Registers
The PCI interface presents a type 0 configuration register set in configuration space, with the standard extension for power management. Table 11 summarizes the PCI configuration space registers. Table 11 PCI Configuration Space Registers
Address Offset 00h 04h 08h 0Ch 10h 14h 18h 1Ch 20h 24h 28h 2Ch 30h 34h 38h 3Ch 40h 44h Configuration register 31 Device ID Status Class code BIST Header type Latency timer Base address register 0 (BAR0) Base address register 1 (BAR1) Base address register 2 (BAR2) Base address register 3 (BAR3) Base address register 4 (BAR4) Base address register 5 (BAR5) Cardbus CIS pointer Subsystem device ID Expansion ROM base address register RFU RFU Max_lat PM_Data Min_gnt PMCSR_BSE Interrupt pin Next Ptr (always 0) Interrupt line Cap_ID (always 0) Power management capabilities (PMC) Capabilities pointer Subsystem vendor ID 24 23 16 15 Vendor ID Command Revision ID Cache line size 8 7 0
PMC Control/Status register (PMCSR)
Device ID Register
Bits Description 1--parity error, even if parity error handling is disabled by bit 6 in the Command register Set whenever the device asserts SERR#. 0 0 Set whenever the device terminates a transaction with Target-Abort. Device select timing. Target access timing of the function via the DEVSEL# output. This device is a medium speed target device (01b) 0 0 0 1 Reflects the interrupt state in the device/function. INTA# is only asserted when the Interrupt Disable bit in Command is 0 & this Interrupt Status bit is a 1. Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Page 11
This register is read-only via configuration accesses, and returns the current value of the DID register (see section 3.4 for details of this and other PCI set-up registers).
15
14 13 12 11
Vendor ID Register
This register is read-only via configuration accesses, and returns the current value of the VID register.
10:9
Status Register
This register records information on the PCI interface state, as described in the PCI specification. Write 1 to bits 11, 14 and 15 to clear them, all others are read-only.
8 7 5 4 3
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Command Register
This register enables certain features of the PCI interface.
Bits 10 Description 1--disables INTA# assertion 0--enables INTA# assertion After RST# is 0 0 1--enables. the function to report address parity errors via SERR# 0 1--enables the function to report parity errors via PERR# 0 0 0 0 Controls the response to memory space accesses. 1--allows the device respond to the PCI bus memory accesses as a target Controls the response to I/O accesses. 1--allows the device respond to the PCI bus I/O accesses as a target
Latency Timer
Read-only register always returns 00h. (Not relevant for target-only PCI devices).
Cache Line Size
This register is read-only and always returns 00h. (The device does not support cache line wrap mode)
9 8 7 6 5 4 3 2 1
Base Address Register 0
This register sets the PCI base address in memory space for access to local configuration registers. The register has bits 31-7 writable, and the remainder of the bits are always 0. This forms a request for 128 bytes of memory space with a 32-bit address, marked as non-prefetchable. Accesses made to the memory range defined by this BAR map to internal configuration registers at internal addresses 00h-07h.
0
Base Address Register 1
This register sets the PCI base address in I/O space for access to local configuration registers. The register has bits 31:7 writable; the remainder are always 01h. This forms a request for 128 bytes of I/O space. Accesses made to the I/O range defined by this BAR map to internal configuration registers at internal addresses 00h-07h.
Class-Code Register
This register is read-only via configuration accesses, and returns the current value of the PCC register.
Revision ID Register
This register is read-only via configuration accesses, and returns the current value of the REV register.
Base Address Register 2
This base address register is for a mapping of 64 bytes in I/O space. Accesses made to the I/O range defined by this BAR map to internal UARTs at internal addresses 80h-BFh.
BIST Register
This byte always returns 00h, and writes to the byte are ignored, as there is no BIST function.
Base Address Register 3
This base address register is for a mapping of 16 bytes in I/O space. Accesses made to the I/O range defined by this BAR map to unused internal addresses C0h-CFh.
Header Type
This byte always returns 00h, indicating a type 0 header and a single-function device. Writes to the byte are ignored.
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Base Address Register 4
This base address register is for a mapping of 64 bytes in 32-bit memory space (nonprefetchable memory). Accesses made to the memory range defined by this BAR map to internal UARTs at internal addresses 80h-BFh.
Interrupt Pin Register
This register is read-only via configuration accesses, but may be set to either 00h or 01h using local-register access via BAR0, BAR1 or EEPROM configuration. It is set to 01h following a PCI reset.
Base Address Register 5
This base address register is for a mapping of 16 bytes in 32-bit memory space (nonprefetchable memory). Accesses made to the memory range defined by this BAR map to internal addresses C0h-CFh.
Interrupt Line Register
This register is read-write accessible via configuration accesses. It is set to 00h following a PCI reset.
Power-Management Registers
The Power Management Capabilities register is read-only via configuration accesses. It provides the host system with information on the power-management capabilities of the PCI device and returns the current value of the PMC register. It is set to a generic-configured value following a PCI reset. This register is mostly just for the passing of power management information to the host system, but two of the fields also have an affect on the operation of the block:
Bits 10 Description 0--writing 10b to the PowerState bits in PMCSR (see below) leaves PowerState unchanged 0--writing 01b to the PowerState bits in the PMCSR (see below) leaves PowerState unchanged
Cardbus CIS Pointer
Hard-wired to zero, as this device is not for use in CardBus applications.
Subsystem Device ID Register
This register is read-only via configuration accesses, and returns the current value of the SDID register.
Subsystem Vendor ID register
This register is read-only via configuration accesses, and returns the current value of the SVID register.
9
Expansion ROM Base Address Register
Hard-wired to zero.
Capabilities Pointer
This register is read-only and always returns 40h, as this is where the power management registers are located.
Max_lat Register
Read-only register which always returns 00h. (Not relevant for target-only PCI devices)
Min_gnt Register
Read-only register which always returns 00h. (Not relevant for target-only PCI devices)
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The Power Management Control/Status register (PMCSR) has a mixture of read-only, read/write and read/clear-on-write bits.
Bits 15 Description Set when the function would assert the PME# signal if bit 8 is enabled. Writing 1 clears it & causes the function to stop asserting PME#. Writing 0 has no effect. Cleared on PCI reset Read-only scaling factor to be used when interpreting the value of the Power Management Data register. The value and meaning of this field will depend on which data value has been selected using bits 12:9 Read/write field used to select which data is to be reported through the Data register & bits 14:13. Resets to 0 1--enables PME# 0--disables PME# (default) Determines the current power state of a function & sets it into a new power state using the values below. 00b--D0 01b--D1 10b--D2 11b--D3 If software attempts to write an unsupported, optional state to this field (i.e. D1 when D1_Support is not set, or D2 when D2_Support is not set), the write operation completes normally on the bus; however, the data is discarded and no state change occurs. Reset value 00b
OX16PCI958 DATA SHEET
The Power Management Data register at offset 47h is read-only, and returns a value which depends on which data value has been selected using PMCSR [12:9].
14:13
12:9
8 1:0
The Power Management Bridge Support Extensions register at offset 46h is read-only, and always returns the value 00h.
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3.4.
PCI Set-up Registers
Table 12 lists the PCI set up registers. Table 12 Address Map
Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h PMC7:0 PMC15:8 PMD(0) PMD(1) PMD(2) PMD(3) PMD(4) PMD(5) PMD(6) PMD(7) PMDS(3:0) PMDS(7:4) Register VID7:0 VID15:8 DID7:0 DID15:8 REV PCC7:0 PCC15:8 PCC23:16 SVID7:0 SVID15:8 SDID7:0 SDID15:8 PIP Register description Vendor ID, lower byte Vendor ID, upper byte Device ID, lower byte Device ID, upper byte PCI silicon revision PCI class code, programming interface byte PCI class code, subclass code byte PCI class code, base class code byte Subsystem Vendor ID, lower byte Subsystem Vendor ID, upper byte Subsystem Device ID, lower byte Subsystem Device ID, upper byte Interrupt pin (bit 0 only used) RFU Power management capabilities, lower byte Power management capabilities, upper byte Power management data, for when data_select=0 Power management data, for when data_select=1 Power management data, for when data_select=2 Power management data, for when data_select=3 Power management data, for when data_select=4 Power management data, for when data_select=5 Power management data, for when data_select=6 Power management data, for when data_select=7 Power management data_scale, for when data_select=0, 1, 2, 3 Power management data_scale, for when data_select=4, 5, 6, 7 Default Value 15h* 14h* 38h* 95h* 01h 00h 02h 07h 15h* 14h* 00h* 00h* 01h 02h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
* Ensure these registers are written by the configuration EEPROM. Most of these registers simply hold values which are presented in read-only registers in PCI configuration space (see section 3.3). PMDS(3:0) and PMDS(7:4) contain eight 2-bits, packed as shown below, returned as a value for bits 14:13 in PMCSR when PMCSR [12:9] = n where n references PMDSn (see section 3.3).
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4. UART FUNCTION
Each UART in the OX16PCI958 is identical. The depth of the FIFOs is 32 bytes. Each UART converts between RS232-format serial data on separate transmit and receive lines, and byte-wide I/O writes and reads on the host interface. Malformed incoming serial data is flagged along with the data in the receive FIFO. The state of the UART can be found at any time by reading status registers, and modem control (handshaking output) lines can be individually controlled. Although polled-mode operation is possible, the UARTs will usually be operated on a hostinterrupt basis. The interrupt system is designed to allow efficient handling of interrupt service requests from the UART, for example by using the prioritised interrupt identification register, readable FIFO levels, and tuneable FIFO trigger levels. The internal transmitter and receiver logic runs at a programmable synchronisation factor of 4x, 8x, or 16x the serial baud rate. This internal clock is generated by dividing a reference clock by an integer divisor from 1 to (216 - 1) and a fractional divisor from 8/8 to 255/8. more than one event needs servicing, the most urgent one is indicated. A "transmitter FIFO empty" interrupt is cleared as soon as the IIR is read, so if there is no data waiting to be transmitted then no further action is needed. To restart the flow of transmitted data, the usual practice is for the user-mode part of the device driver to add the data to the software transmit queue and then kick-start transmission by re-writing to the IER with its current value (with bit 0 set). This will re-enable the "transmitter FIFO empty" interrupt and the interrupt handler will handle the transfer of transmit data to the UART, pushing another block every time the FIFO becomes empty.
4.2.
Accessible Registers
The internal registers of the UART are listed in Table 13, organized by function with both full name and mnemonic. Table 13 Accessible UART Registers
Register Selection Indexed register select Line control (bit 7) Safety catch control UART Data Receiver buffer Transmitter holding UART Control LSB divisor latch MSB divisor latch Interrupt enable FIFO control Line control Modem control Synchronisation factor Clock prescaler UART configuration Port control Receive FIFO flow-control trigger Receive FIFO interrupt trigger Transmit FIFO interrupt trigger Mnem. IRSR LCR SCC Mnem. RBR THR Mnem. DLL DLM IER FCR LCR MCR SFR CPR UCR PCR RFTR RITR TITR
4.1.
Programming
To prepare the UART for communication, it is necessary to first configure the serial channel using the control registers LCR, SFR, DLL and DLM. These set the number of data and stop bits, the parity setting and the baud rate. These registers can be changed at any time, but if data is being received or transmitted then corruption of the serial data is likely to occur. It is also a good idea to enable FIFOs using FCR and UCR, to decrease the number of data-transfer services the UART will require. The trigger levels can also be set at this stage using RFTR, RITR and TITR, although the TL16C550-compatible method using FCR7:6 will still work. If appropriate, auto-flow control may be enabled by writing the MCR, and the same register sets the initial state of the output handshaking lines. Once the serial channel is configured, interrupts can be enabled by writing IER and setting MCR3. The interrupt handler can read the IIR to determine what type of event needs servicing: the interrupt types are prioritised so that if
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UART Status (read only) Interrupt identification Line status Modem status Chip ID register Receive FIFO level Transmit FIFO level Build & Test Scratch pad Inverted scratch pad Mnem. IIR LSR MSR CIDR RFLR TFLR Mnem. SCR ISCR
OX16PCI958 DATA SHEET
Individual bits within the registers are referred to by the register mnemonic with the bit number appended. For example, LCR7 refers to bit 7 of the line control register. The register accessed when an I/O read or write is performed depends on the bits 2:0 of the internal address, the divisor latch access bit (DLAB, which is LCR7), and the Indexed Register Select register (IRSR). Registers with A2:0 from 0 to 7 are accessed through BAR2 or BAR4, and those with A2:0 from 8 to 9 are accessed through BAR3 or BAR5. See section 3.1 for details. The transmitter holding register and receiver buffer register are used to transfer data for transmission and received data respectively. These are eight-bit registers, but the serial data may be 5, 6, 7 or 8 bits long: data is rightjustified and padded with zeroes on the left. The UART always receives and transmits bit 0 first. The THR and RBR can be accessed at the same time as serial data transmission and reception are taking place, because the serializer and deserializer are separate from the data buffers/FIFOs.
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Table 14 shows how to select the required UART register. Table 14 Register Selection
IRSR X X X X X X X X X X X X X X 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 >17 DLAB 0 0 1 1 0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X A2:0 0 0 0 1 1 2 2 3 4 5 6 6 8 9 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Mnemonic RBR THR DLL DLM IER IIR FCR LCR MCR LSR MSR IRSR PCR SCC SCR ISCR CIDR SFR UCR RFLR TFLR RFTR RITR TITR CPR WER Register
OX16PCI958 DATA SHEET
Receiver buffer register (read only) Transmitter holding register (write only) LSB divisor latch MSB divisor latch Interrupt enable register Interrupt identification register (read only) FIFO control register (write only) Line control register Modem control register Line status register (read only) Modem status register (read only) Indexed register select register (write only) Port-control: alternate control for CPR Safety-catch control Scratch pad register Inverted scratch pad register Chip ID register (read only) Synchronisation factor register Reserved for compatibility Reserved for compatibility UART configuration register Reserved for compatibility Receive FIFO level register Transmit FIFO level register Reserved for compatibility Reserved for compatibility Reserved for compatibility Receive FIFO flow-control trigger register Receive FIFO interrupt trigger register Transmit FIFO interrupt trigger register Clock prescaler register Wake event enable register Reserved for future use - do not read or write
X = irrelevant, 0 = low level, 1 = high level The system programmer, using the host, can access any of the UART registers, as summarized in Table 15.
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Table 15 UART Register Summary
Register Mnemonic, Access RBR (read only) A=0, DLAB=0 THR (write only) A=0, DLAB=0 DLL A=0, DLAB=1 DLM A=1, DLAB=1 Register Bit Number Bit 7 Data Bit 7 (MSB) Bit 6 Data Bit 6 Bit 5 Data Bit 5 Bit 4 Data Bit 4 Bit 3 Data Bit 3 Bit 2 Data Bit 2 Bit 1 Data Bit 1 Bit 0 Data Bit 0 (LSB)
Data Bit 7
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11 (EDSSI) Enable modem status interrupt DMA mode select (ignored) Interrupt ID Bit 3 (PEN) Parity enable OUT2 (interrupt enable) Framing Error (FE) (DCD) Delta data carrier detect Bit 3
Bit 10 (ERLSI) Enable receiver line status interrupt
Bit 9 (ETHREI) Enable transmitter buffer empty interrupt
Bit 8 (ERBFI) Enable received data available interrupt
IER A=1, DLAB=0
0
0
Sleep Low power mode enable enable (ignored) (ignored)
FCR (write only) A=2 IIR (read only) A=2 LCR A=3 MCR A=4 LSR (read only) A=5 MSR (read only) A=6 IRSR (write only) A=6 PCR A=8 SCC A=9 SCR A=7, IRSR=0 DS-0022 Nov 05
Receiver Trigger (MSB) FIFOs Enabled (DLAB) Divisor latch access bit 0 Error in Receiver FIFO (DCD) Data carrier detect Bit 7
Receiver Trigger (LSB) FIFOs Enabled
0
0
Transmitte Receiver FIFO r FIFO FIFO reset enable reset Interrupt ID Bit 2 Interrupt ID Bit 1 0 if interrupt pending (WLSB0) Word length select bit 0 DTR Data Ready (DR)
0
0 (EPS) Even parity select Loop Break Interrupt (BI) (CTS) Clear to send Bit 4
Set break
Stick parity
(WLSB1) (STB) Word Number of length stop bits select bit 1 OUT1 Parity Error (PE) (TERI) Trailing edge ring indicator Bit 2 RTS Overrun Error (OE)
0
AFE
Transmit Transmitte holding r Empty register (TEMT) (THRE) (RI) Ring indicator Bit 6 (DSR) Data set ready Bit 5
(DSR) (CTS) Delta data Delta clear set ready to send Bit 1 Bit 0
RFU Indexed reg safety catch Bit 7
RFU RFU Bit 6
Clock Clock Hold CTS select bit 1 select bit 0 RFU Bit 5 RFU Bit 4 RFU Bit 3
RFU RFU Bit 2
RFU RFU Bit 1
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Register Mnemonic, Access ISCR A=7, IRSR=1 CIDR (read only) A=7, IRSR=2 SFR A=7, IRSR=3 UCR A=7, IRSR=6 RFLR (read only) A=7, IRSR=8 TFLR (read only) A=7, IRSR=9 RFTR A=7, RSR=13 RITR A=7, RSR=14 TITR A=7, RSR=15 CPR A=7, RSR=16 WER A=7, RSR=17 Register Bit Number Bit 7 Bit 7 Bit 6 Bit 6 Bit 5 Bit 5 Bit 4 Bit 4 Bit 3 Bit 3
OX16PCI958 DATA SHEET
Bit 2 Bit 2
Bit 1 Bit 1
Bit 0 Bit 0
0
0
0
1
0
0
0
0
RFU RFU Error in Receiver FIFO Bit 7
RFU RFU
RFU RFU
SF=16 RFU
SF=8 RFU
SF=4 RFU
RFU Enable deep FIFOs Bit 1
RFU Force AFC on Bit 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RFU RFU RFU Bit 7 INT
Bit 6 Bit 6 Bit 6 Bit 6 RFU
Bit 5 Bit 5 Bit 5 Bit 5 RFU
Bit 4 Bit 4 Bit 4 Bit 4 SIN#
Bit 3 Bit 3 Bit 3 Bit 3 DCD
Bit 2 Bit 2 Bit 2 Bit 2 TERI
Bit 1 Bit 1 Bit 1 Bit 1 DSR
Bit 0 Bit 0 Bit 0 Bit 0 CTS
In this column, `A' refers to the decimal value of the internal address bus. disabled.
These bits are always 0 when FIFOs are
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Table 19 Effect of RESET on UART FIFOs
Master Reset
The UARTs are reset when PCI RESET# is asserted. Table 16 and Table 17 summarize the effect of reset on the UART circuits. Table 16 Effect of RESET on UART Signals
UART Signal DTR# RTS# SOUT Reset control Reset Reset Reset Signal Reset State High High High
FIFO Receiver FIFO Transmitter FIFO
Reset Control Reset FCR1-FCR0 FCR0 Reset FCR1-FCR0 FCR0
FIFO Reset State FIFO empty
FIFO empty
Serial Data Format
A 0 in RBR or THR corresponds to a logic low on SIN or SOUT, and a 1 in RBR or THR corresponds to a logic high on SIN or SOUT. Bit 0 is always the least significant bit (LSB) and is the first bit to be serially transmitted or received. A start bit or line break state corresponds to a logic low on SIN or SOUT, and a stop bit or inter-byte marking state corresponds to a logic high on SIN or SOUT.
Table 17 Effect of RESET on UART Registers
UART Register LSR MCR IER FCR IIR LCR TFTR MSR IRSR SCR LSB & MSB RBR THR RFTR RITR UCR WER Register reset state Bits 7,4,3,2,1,0 cleared Bits 6 & 5 set All bits cleared Note bits 7:6 permanently cleared All bits cleared Note bits 7:6 permanently cleared All bits cleared Bits 7,6,3,2,1 cleared Bit 0 is set All bits are cleared All bits are cleared Bits 3-0 cleared Bits 7-4 input signals All bits cleared All bits cleared All bits cleared All bits cleared All bits cleared All bits cleared All bits are cleared All bits are cleared All bits are cleared
4.3.
Transmitter/Receiver Section
The status of the receiver is given by the Line Status Register (LSR). The control of the receiver section and format of the data characters such as number of data bits, parity, etc is controlled by the Line Control Register (LCR). Note if parity is used (LCR3) then the polarity of parity LCR4 is required. As serial asynchronous data is fed into the receiver serial data input terminal SIN, the UART continually looks for a high-to-low transition. Upon detection of the transition, an internal counter is reset and counts the SFx clock input to SF/2, which is the centre of the start bit. (SF is the Synchronisation Factor) The receiver is prevented from assembling a false data character caused by noise on the SIN input, by verification of the start bits. Note: The start bit is valid only if SIN is still low. The UART receiver section contains a Receiver Buffer Register (RBR) which is a FIFO and a Receiver Deserializer Register (RDR). Data fed into the receiver serial data input terminal SIN is deserialized by the RDR and is fed into RBR. The control of the receiver section and format of the data characters such as number of data bits, parity, etc is controlled by LCR. Note if parity is used (LCR3) then the polarity of parity LCR4 is required. The receiver timing is supplied by the baud clock generator.
Table 18 Effect of RESET on UART Interrupts
Interrupt Type modem status changes receiver data ready RCVR errors THRE Reset Control Interrupt Reset State Low Low Low Low
Reset/Read MSR Reset/Read RBR Reset/Read LSR Reset/Read IIR/Write THR
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In FIFO modes, FCR is used to enable and reset the receiver FIFO and also can be used to set data trigger levels for when interrupts are generated. In non FIFO mode (16C450 style), when the received data available interrupt is enabled, an interrupt is generated when a character is placed in the receiver buffer register. When RBR is read, the interrupt is cleared.
Bits 3 Description
OX16PCI958 DATA SHEET
1--a parity bit is generated between the last data word bit & stop bit in data transmitted & checked by the receiver 0--no parity is selected; see Table 20 Specifies either one or two stop bits in each transmitted character. 0--one stop bit is generated in the data 1--11/2 or 2 stop bits are generated in the data: see Table 22. The receiver clocks only the first stop bit, regardless of the number of stop bits selected These two bits specify the number of bits in each transmitted or received serial character; see Table 21
2
Transmitter Holding Register & Multiplexer Register (THR & TMR)
The UART transmitter section contains a Transmitter Holding Register (THR), which is a FIFO, and a transmitter multiplexer register (TMR). THR receives data off the internal data bus and moves it into the TMR, while the transmitter is idle, which serializes the data and outputs it to the transmitter data serial output terminal SOUT. The transmitter timing is supplied by the baud clock generator. In FIFO modes, FCR is used to enable and reset the transmitter FIFOs and can be used to set data trigger levels for when interrupts are generated. For more details see Section 4.2. In non FIFO mode (16C450), when the transmitter holding register empty interrupt is enabled, an interrupt is generated when THR is empty. When a character is loaded into the register, the interrupt is cleared.
1:0
Table 20 Parity Selection
LCR5:3 XX0 001 011 101 111 Description No parity Odd parity Even parity Set parity Cleared parity
Table 21 Word Length Selection
LCR1:0 00 01 10 11 Description Word length is 5 bits Word length is 6 bits Word length is 7 bits Word length is 8 bits
Table 22 Stop Bit Length Selection
LCR2:0 0XX 100 101 110 111 Description 1 stop bit generated 11/2 stop bits generated 2 stop bits generated 2 stop bits generated 2 stop bits generated
Line Control Register (LCR)
LCR controls the format of the data character and is applicable to both transmitter and receiver. The LCR is read-writable. Its contents are described below.
Bits 7 Description Divisor latch access bit (DLAB) 1--enables access to DLL & DLM 0--enables access to IER, THR &RBR 1--SOUT is forced to the spacing state (low) 1--If LCR3 is 1, parity bit transmission & reception is the state opposite to LCR4 value. If LCR4 is 1, even parity enabled. (or cleared parity enabled, if LCR5 is 1) 0--odd parity enabled (or set parity enabled, if LCR5 is 1) This forces parity to a known state 1--even parity enabled. (or cleared parity is enabled, if LCR5 is 1) 0--odd parity enabled (or set parity enabled, if LCR5 is 1).
Use the following steps to create a line break: Note: no invalid characters are transmitted because of the break. 1. When THRE empty status occurs, load a zero byte 2. After the next THRE, set the break 3. When TEMT is set to high, wait for the transmitter to be idle 4. Clear the break when the transmission has to be re-established.
6 5
4
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Line Status Register (LSR)
Read-only register that indicates the status of serial data reception.
Bits 7 Description Set when a character with a parity, framing, or break error enters the FIFO. Cleared when LSR is read & no FIFO characters have an error flag set. Set when no character is being transmitted, & no characters queued for transmission in THR or transmit FIFO When FIFOs are disabled, set when THR is empty & the UART is ready for a new character to be written to it. When FIFOs are enabled, set when the FIFO is empty Break interrupt indicator. A break interrupt or line break occurs when SIN is held low for longer than the normal transmission time for the start, data, parity & stop bits configured. The interrupt, whatever its length, is queued like a received character whose data bits are all cleared & a BI flag is attached to it in the receive FIFO. 1--the next character to be read from the RBR has its BI flag set The UART initially attempts to interpret the interrupt as a received character, so LSR3 is set because there was no valid stop bit & LSR2 may be set if parity bits are enabled Framing error indicator. When a character without the expected stop bit is received, a framing error flag is attached to the character in the receive FIFO. 1--the next character to be read from the RBR has its FE flag set When a character is received with a framing error, the UART assumes that character synchronization is lost & attempts to resynchronize by assuming that what was sampled as the stop bit of a character is actually the start bit of the next character Parity error indicator. When a character is received that does not have the expected value where the parity bit is expected, a parity error flag is attached to the character in the receive FIFO. 1--the next character to be read from the RBR has its PE flag set Overrun error indicator. Set when a character is received & nowhere for it to be stored, i.e. the receive FIFO is full. The character & associated error flags are lost. Cleared when LSR is read Data ready indicator. Set when a character can be read from the RBR or receive FIFO
Interrupt Enable Register (IER)
IER controls independent enable/disable for UART interrupt sources. A disabled source does not cause assertion of IREQ# and its code does not appear on the IIR.
Bit 3 2 1 0 Description 1--enables modem status interrupts 1--enables receiver line status interrupts 1--enables transmitter holding register empty interrupts 1--in FIFO modes, enables received data available & character time-out interrupts
6
5
Interrupt Identification Register (IIR)
IIR indicates the interrupt status of the UART and information about the FIFO status. To ensure that the most time-critical interrupt sources are serviced first, IIR returns a code indicating the highest-priority interrupt sources that is currently active. The interrupt sources are prioritized as follows: * * * * * (Highest priority) Receiver line status Receiver character time out Receiver data ready Transmitter holding register empty (Lowest priority) Modem status
4
3
The contents of the IIR are indicated in the table below.
Bits 7:6 3:1 0 Description Set when FCR0 is set, i.e., the UART is in a FIFO mode Identifies the highest-priority interrupt currently active, as indicated in Table 23. Cleared when any interrupt is active; set when no interrupt sources are active
2
1
0
Note: Writes to LSR are ignored, but it is recommended to avoid them because there may be unpredictable results on other UARTs.
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Table 23 Interrupt ID Codes in IIR3:0
Value 3:0 0110 1100 Interrupt Receiver line status Character time-out Priority Level 1 2 Source OE, PE, FE, or BI are set in the LSR During the last four character times, at least one character has been waiting in the receive FIFO, and the FIFO has been inactive. The receive FIFO has reached its trigger level. Clear Mechanism Read LSR Read RBR
0100
Received data available THRE Modem status None
3
Read RBR until FIFO drops below the trigger level Read IIR or write to THR Read MSR -
0010 0000 0001
4 5 None
THRE is set in the LSR: the UART is ready to be given more data to transmit. At least one of the MSR3:0 bits are set, because CTS#, DSR#, RI#, or DCD# have changed No interrupt source active
FIFO Control Register (FCR)
Write only register at the same location as IIR. It enables and clears the FIFOs, and sets the trigger level of the receiver FIFO.
Bits 7:6 2 Description Trigger level for receiver FIFO interrupt 1--all bytes in transmitter FIFO are cleared & counter reset to 0. Does not clear the multiplexer register. Write 1 to clear 1--clears all bytes in the receiver FIFO & resets counter. Does not clear the multiplexer register. Write 1 to clear 1--enables transmit & receive FIFOs; also enables write access to other FCR bits, otherwise they are not programmed. An alteration to this bit clears the FIFOs
4.4. FIFO Interrupt Mode Operation
When the receiver FIFO and receiver interrupts are enabled (FCR0=1, IER0=1, IER2=1), a receiver interrupt occurs as follows: 1. When the FIFO has reached its programmed trigger level, the received data available interrupt is issued to the host. This is cleared when the FIFO drops below its programmed trigger level. 2. In addition to when the FIFO trigger level is reached, and as the interrupt, is cleared when the FIFO drops below the trigger level, the IIR receive data available indication also occurs. 3. The receiver line status interrupt (IIR = 06) holds a much higher priority than the received data available (IIR = 04) interrupt. 4. When a character is transferred from the deserializer to the receiver FIFO, the data ready bit (LSR0) is set. When the FIFO is empty, it is cleared.
1
0
Table 24 Receiver FIFO Trigger Level
FCR7 FCR6 Trigger Level (Bytes) UCR1=0 0 0 0 1 01 04 UCR1=1 01 8 Not empty At least quarterfull At least half-full At least seveneighths full Desc.
1 1
0 1
08 14
16 28
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When the receiver FIFO interrupts are enabled: and receiver
OX16PCI958 DATA SHEET
Table 25 THRE Interrupt Behavior
Event UART reset or IER1 cleared IER written with bit 1 set Effect on THRE interrupt Interrupt cannot occur until IER1 set Interrupt is set immediately if transmit FIFO empty Interrupt set Interrupt cleared Interrupt cleared Interrupt set
1. FIFO time-out interrupt occurs when the following conditions exist: a. A minimum of one character is still present in the FIFO. b. More than four continuous character times have passed (if two stop bits are programmed, the second one is included in this time delay) before a new serial character is received. c. More than four continuous character times have passed since the reading of the FIFO was carried out by the host. This causes a maximum character received to interrupt an issued delay of 160 ms at 300 baud with a 12-bit character.
Transmit FIFO becomes empty IIR read THR written Number of bytes in transmit FIFO drops from TITR+1 to TITR
4.5.
FIFO Polled Mode Operation
If any, or all of the Interrupt enable masks are cleared (IER0, IER1, IER2, IER3, or all four = 0) data and error conditions are still available from the UART by using a polling method. The user application or driver can check transmitter, and/or receiver FIFO status by querying the Line Status Register (LSR). In Polled mode, the FIFOs continue to store data in the expected fashion with the exception that trigger level or time-out flags are not generated.
2. The FIFO interrupt is cleared when a time-out interrupt occurs. When the host reads one character from the receiver FIFO, this causes the timer to reset. The non-occurrence of a time-out interrupt, causes the time-out timer to reset after a new character is received, or after the host reads the receiver FIFO. When the transmitter FIFO and THRE interrupt are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as follows: 3. When the transmit FIFO is empty, it causes the transmitter holding register interrupt [IIR3:0 = 2] to occur. When either the THR is written to, or the IIR is read, this event causes the interrupt to be cleared [IIR3:0 = 1]. 4. A minimum of two bytes in the transmit FIFO are required, at the same instance since the last time that THRE = 1, or this causes the transmit FIFO empty indicator (LSR5 (THRE) = 1) to be delayed one character time minus the last stop bit time. The first transmitter interrupt is instantaneous after changing FCR0 when it is enabled. The behavior of the THRE interrupt is summarized in Table 25 terms of what events cause it to become set and cleared.
Receive FIFO Level Register (RFLR)
This read-only register allows a much faster emptying of the receiver FIFO, by eliminating the need to perform an LSR read before each read of the RBR. If RFLR7 is clear, then the device driver can immediately perform N reads of the RBR, where N is the value given by RFLR6:0.
Bits 7 Description Set if any of the entries in the receiver FIFO has any of its error flags (parity, framing, or break error) set. Cleared when the host reads LSR & there are no subsequent errors in the FIFO. Returns a value between 0 and 31, relating to the number of data entries stored in the receiver FIFO.
6:0
Transmit FIFO Level Register (TFLR)
This read-only register returns a value between 0 and 32, relating to the number of available spaces in the transmit FIFO.
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1 1--RTS# output is forced low 0--RTS# output is forced high The RTS# output of the serial channel can be input into an inverting line driver to obtain the proper polarity input at the modem or data set 1--DTR# output is forced low 0--DTR# output is forced high The DTR# output of the serial channel can be input into an inverting line driver in order to obtain the proper polarity input at the modem or data set
Receive FIFO Flow-Control Trigger Register (RFTR)
This register allows an arbitrary trigger level to be set for auto-RTS flow control (see section 4.7). If the value in this register is non-zero, it is used instead of the trigger level set by FCR7:6. Valid values are 0 to 31.
0
Receive FIFO Interrupt Trigger Register (RITR)
This register allows an arbitrary trigger level to be set for the received data available. If the value in this register is non-zero, it is used instead of the trigger level set by FCR7:6. Valid values are 0 to 31.
Note: MCR7:6 are permanently cleared.
4.6.
Loopback Mode
Transmit FIFO Interrupt Trigger Register (TITR)
This register allows an arbitrary trigger level to be set for the THRE interrupt. Valid values are 0 to 31. If the value in this register is non-zero, then when the number of bytes in the transmit FIFO drops from TITR+1 to TITR the THRE interrupt state will be set. The THRE interrupt is still also generated when the transmit FIFO becomes empty, allowing for the case where less than TITR characters have been written to the transmit FIFO.
The UART enters loopback mode when MCR4 is set, which is useful for testing. Serial data and modem control outputs SOUT, DTR#, RTS#, OUT1#, and OUT2# are forced into an inactive (high) state so that attached devices are not affected. The signals which normally feed these pins are fed into the serial data and modem control inputs (SIN, CTS#, DSR#, DCD#, and RI#), which are disconnected from their input pins. In this mode, data transmitted is immediately received, allowing the host to test the UART transmit and receive data paths. Interrupt control continues to operate based on the state of the looped-back signals rather than the actual SOUT, DTR#, RTS#, OUT1#, and OUT2# input pins.
Internal signal normally controlled by this pin SIN CTS# DTR# DCD# RI# is controlled by the signal which normally goes to this output pin: output is forced high SOUT DTR# DSR# OUT1# OUT2#
loop-back signal `1' output pin
Modem Control Register (MCR)
The MCR controls the interface with the modem or data set as described in Figure 20. MCR can be written and read. The RTS# and DTR# outputs are directly controlled by their control bits in this register (unless the UART is in loopback mode). A high input asserts a low signal (active) at the output terminals. The MCR bits are shown below:
Bit 5 Description 1--enables auto flow-control as described in section 4.7. Auto flowcontrol may also be enabled by UCR0 Provides a local loopback feature for diagnostic testing of the channel. See section 4.6. 1--enables external serial channel interrupt
input pin
1 0
Normal UART behaviour
1 0
4
MCR4
3
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OX16PCI958 DATA SHEET
Bit 7 Description Set when the DCD# input is low. In loopback mode (MCR4 is set), MSR7 reflects the value last written to MCR3 Set when the RI# input is low. In loopback mode, MSR6 reflects the value last written to MCR2 Set when the DSR# input is low. In loopback mode, MSR5 reflects the value last written to MCR0 Set when the CTS# input is low. In loopback mode, MSR4 reflects the value last written to MCR1 1--DCD# input has changed state since the last time the MSR was read 1--RI# input has changed from a low to a high state since the last time the MSR was read. High-to-low transitions on RI# do not affect TERI 1--DSR# input has changed state since the last time the MSR was read 1--CTS# input has changed state since the last time the MSR was read
Modem Status Register (MSR)
MSR allows the state of the modem status lines CTS#, DSR#, RI#, and DCD# to be read by the host. Bits 7-4 of this read-only register reflect the assertion state of the corresponding input pins and bits 3:0 indicate whether changes have occurred on these inputs since MSR was last read. When the UART is operating under interrupts, the host can be notified of changes in the modem status lines by enabling modem status interrupts (set IER3), in which case a priority-5 interrupt is generated when any of MSR3:0 become set. The interrupt is generated whether the setting of MSR3:0 is caused by changes on the modem status lines or by changes of MCR3:0 in loopback mode.
6
5
4
3 2
1 0
4.7.
Auto Flow Control
Auto flow control consists of two functional parts: auto-CTS and auto-RTS. These features allow the flow of serial data to be throttled, preventing data loss due to receive buffer overruns, without relying on fast interrupt service. RTS# and CTS# are often used for flow control, but if the host has to perform that function then delays in servicing interrupts can mean that the flow control is not quick enough, and data can be lost. When a pair of UARTs are connected that both have auto flow control enabled, then loss-free data transfer is possible whatever the interrupt latencies of the host systems. The RTS# output of the receiving UART must be connected to the CTS# input of the transmitting UART, as shown below. Usually a full-duplex link will be used and so the diagram below will be only half the system, with both UARTs having a transmitting and a receiving side and being connected symmetrically. Figure 1 Auto Flow Control (Auto-RTS & Auto-CTS) Example
Transmitting UART Parallel to Serial Flow Control SOUT SIN Receiving UART Serial to Parallel Flow Control
Transmit FIFO
Receive FIFO
CTS#
RTS#
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OX16PCI958 DATA SHEET
4.7.1. Auto-RTS
Auto-RTS attempts to control the flow of serial data in to the UART. When enabled, it automatically signals to a connected device that it should stop transmitting, because there is a risk of the receive FIFO overrunning. This is done by making the state of the RTS# output dependent on the level of the receive FIFO: RTS# is asserted when the receive FIFO is below a certain trigger level, and deasserted when the receive FIFO is at or above that trigger level. The OX16PCI958 UARTs support the setting of the trigger level to four predefined levels using FCR7:6 and also allow a precise value to be set using RFTR.
Synchronization Factor Register (SFR)
The UART uses an internal clock that is faster (by a fixed integer factor) than the baud rate selected. The factor by which it is faster is called the synchronisation factor (SF). Received data is clocked into the UART every SF clock cycles, and the position of these enabled cycles is selected so as to clock in data from as close to the middle of each serial bit as possible. A higher value of SF gives a sampling time which is closer to the centre of the bits, and hence gives greater tolerance of line noise, but also gives higher power consumption and a lower maximum baud rate. This register allows the programmer to select the synchronisation factor used. Allowed values for writing to this register are 04h, 08h, and 10h.
4.7.2. Auto-CTS
Auto-CTS controls the flow of serial data from the UART. When enabled, the transmitter will not start transmitting a new data byte unless the CTS# input is asserted. If data transmission is stopped in this way, it restarts as soon as CTS# is asserted. The UART never sends partial data bytes.
Programmable Baud Rate Generator
The internal clock used by the UART transmit and receive units is generated by taking the clock input fed into XTALI and dividing it first by the global clock divider, then by a prescaling factor, and then by a 16-bit integer value (the "divisor"). The baud rate calculation is:
baud rate = XTALI input freq / (global predivider x (CPR/8) x divisor x SF)
4.7.3. Enabling Auto-RTS & Auto-CTS
It is possible to have neither auto-RTS nor autoCTS enabled (with manual control of RTS#), or both enabled, or auto-CTS enabled with RTS# held deasserted. Auto-RTS and auto-CTS are activated by setting bits MCR5 and MCR1, but auto flow control is also affected by MCR1, MCR4, and UCR0.
The divisor is stored in two 8-bit divisor latches. Setting the divisor latches is a necessary step in the initialization of the UART before data can be transmitted or received. Loading a divisor of zero (all bits cleared in DLL and DLM) stops the clocking of the receiver and transmitter, i.e. it gives a baud rate of zero. No serial data is transmitted or received, no data enters the receive FIFO or leaves the transmit FIFO. The level on SOUT can still be changed by writing LCR6, and all other UART functions continue to operate.
Clock Prescaler Register (CPR)
This register allows more fine-grained control over the baud rate than is possible using the divisor alone. Before being divided by the divisor value stored in DLL and DLM, the clock is prescaled, being divided by (CPR/8). Valid values of the CPR are 8 to 255 inclusive. The reset value of the CPR is 8, i.e. the prescaler has no effect. This register is automatically set to 8, 16 32 or 64 when the PCR is written.
Port Control Register (PCR)
Bit 3 allows the CTS input of the UART to be held in a `true' state, regardless of the state of the CTS# input pin: see Table 26. Table 26 Hold CTS Values
Value 0 1 Description CTS reflects state of CTS# pin CTS held true
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Table 27 Chip Identification Code Values
Value 00-0Fh 10h 11-1Fh Description Reseved UART conforming to this specification Reserved for devices with register sets compatible with the OX16PCI958. Device drivers may assume the device conforms with this specification, though additional features may also be present. Reserved
4.8.
Chip Type Identification
To determine whether a UART is a OX16PCI958 UART, and to clear the extended registers safety catch: * * * * * Ensure that bit 4 of IER is cleared Write 80h to LCR Write 00h to DLM Set X=23h Repeat the following 42 times: * * * * Write the value X to DLM Set X=X x 2 Set bit 0 of X to the exclusive-or of bit 7 and bit 6 of X
others
UART Configuration Register (UCR)
Read-write register with reset value taken from the configuration EEPROM.
Bit 2 Description 1--UART generates transmit-buffer-empty interrupts until < 16 spaces are left in the transmit FIFO, or no data is written 1--FIFOs are always 32 deep when FCR0 is set 1--when MCR4 is cleared, auto flow control is always on, even when the driver does not enable it (should only be used if the attached device is using RTS-CTS handshaking for flow control)
If IER4 is set, the chip is an OX16PCI958 or a future device with the same extendedregister system. Write 2 to IRSR and read CIDR to identify the device type. If IER4 is clear, the chip is not a known device.
Do not make any other read or write access to the UART while writing the sequence of values to the DLM. The sequence should be: 00h, 23h, 47h, 8Fh, 1Eh, 3Ch, 79h, F2h, E4h, C8h, 91h, 22h, 45h, 8Bh, 16h, 2Ch, 59h, B3h, 67h, CEh, 9Dh, 3Ah, 75h, EAh, D4h, A9h, 53h, A7h, 4Fh, 9Fh, 3Eh, 7Dh, FAh, F4h, E8h, D0h, A1h, 43h, 87h, 0Eh, 1Ch, 38h, 71h.
1 0
Table 28 Operation when UCR0 is Cleared
MCR5 1 MCR1 1 0 X Flow Control Configuration Auto-RTS# & auto-CTS# enabled (auto flow control enabled) Auto-CTS# only enabled Auto-RTS# & auto-CTS# disabled
Extended Registers Safety Catch
Some host systems may violate the TL16Cx50 specifications and write to the MSR, which sets IRSR in the OX16PCI958 UART and could lead to failure due to an apparently failed scratch register or corruption of the extended registers. To prevent this problem, the IRSR is protected by a safety catch. After any reset of the UART a safety-catch is engaged which causes writes to the MSR/IRSR address to be ignored. To clear the safety catch and enable access to the extended register set, an OX16PCI958aware device driver may perform the chip type identification sequence to enable writes to the IRSR until the next UART reset. Alternatively, the safety catch can be written and read directly at bit 7 of the SCC register.
1 0
Table 29 Operation when UCR0 is Set
MCR4 0 MCR5 X MCR1 1 Flow Control Configuration Auto-RTS# and autoCTS# enabled (auto flow control enabled) Auto-CTS# only enabled, RTS# deasserted Auto-RTS# and autoCTS# enabled (auto flow control enabled) Auto-CTS# only enabled Auto-RTS# and autoCTS# disabled
0
X
0
1
1
1
1
1 0
0 X
Chip ID Register (CIDR)
Read-only register which provides an identification code so software can distinguish between versions of the OX16PCI958, or future components with a similar interface. Codes are given in Table 27
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Scratchpad Register (SCR)
The 8-bit read/write scratch register has no affect on either channel in the UART. It is intended to be used by the programmer to hold data temporarily.
4.9.
SISR Function
Inverted Scratchpad Register (ISCR)
Writes to this register set the scratchpad register. Reads return the current scratch register value with all bits inverted.
A "Shared Interrupt Status Register" (SISR) function can be enabled. The purpose of this function is to help device drivers arbitrate between the multiple UARTs that may be requesting an interrupt service. The function consists of a single 8-bit read-only register. The binary value of this value will either be FFh, indicating that there is no UART requesting an interrupt service, or a value from 0 to 7 inclusive indicating the number of the UART that the device driver should service next. This value is determined using a round-robin algorithm. There is no requirement to use the SISR function, UARTs may be serviced in any order-- the SISR is only included as an aid to fair servicing of the ports.
Wake Event Enable Register (WER)
This register controls the serial port events that can trigger a wake event, e.g. on the PCI bus. One wake event source requires the UART's clock to be running, but five are entirely asynchronous and require no clock.
Bit 7 Description 1--a wake event is generated whenever an enabled interrupt event occurs. Requires the UART clock to be running 1--a wake event tis generated whenever SIN goes low 1--a wake event is generated whenever DCD# has a changed state since the last time the UART was clocked 1--a wake event is generated whenever RI# goes low 1--a wake event is generated whenever DSR# has a changed state since last time the UART was clocked 1--a wake event is generated whenever CTS# has a changed state since the last time the UART was clocked
4 3
2 1
0
The wake event from the UART is a rising edge on the wake output: it is the job of external circuitry to latch this signal if needed.
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5. EEPROM
5.1. The EEPROM Reader
After the host bus RESET signal has been asserted and then released, the OX16PCI958 reads the attached Microwire-type serial EEPROM to obtain configuration information. The EEPROM must be in 16-bit mode, and connected for 3-wire operation, as shown in Figure 2. Figure 2 Example Circuit for EEPROM Connection
OX16PCI958
VDD ORG EEDIO DI
DO EECK EECS SK CS
FM93C46A EEPROM
The EEPROM must be set up to provide 16-bit data, e.g. by tying the ORG pin high on an AT96C46. Any serial EEPROM with a 16-bit data and Microwire-compatible read instruction, where the number of address bits is either 6 or 8, should be suitable for use with the OX16PCI958. The EEPROM does not have to have a sequential read feature. This means that most 93C46, 93C56 and 93C66 parts should be suitable. Figure 3 EEPROM Read Waveform
EECS
EECK
DI
1
1
0
An
An-
A1
A0 0
DO
D15
D1
D0
EEDIO
X
1
1
0
An
An-
A1
A0
0 D15
D1
D0
X
The interface timings are designed to be suitable for EEPROMs with maximum clock frequencies down to 250 kHz. The EEPROM reader unit sets up EECS and EEDIO 70 PCI clock cycles before generating a rising edge on EECK, and it samples EEDIO 70 PCI clock cycles after the EECK rising edge. The EECK clock cycle lasts for 140 PCI clock cycles, giving an EEPROM clock rate of 238 kHz when the PCI clock is running at 331/3 MHz.
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Figure 4 EEPROM Signal Timings During Initialization
Type Generated Generated Generated Generated Generated Generated Generated Generated Allowed Allowed Allowed Signal EECK EECK EECK EECS EECS EECS SBDIO SBDIO SBDIO SBDIO SBDIO Timing Cycle period Low time High time Set-up before SK Hold after SK CS low time Set-up before SK Hold after SK Delay to valid after SK Hold after SK Delay to high-Z after SK Min 4140 2040 2040 2040 2040 2040 2040 2040 Nom 140 x TPCI 70 x TPCI 70 x TPCI 70 x TPCI 70 x TPCI 70 x TPCI 70 x TPCI 70 x TPCI 70 x TPCI 70 x TPCI 70 x TPCI 2040 2040 2040 Max Unit ns ns ns ns ns ns ns ns ns ns ns
These values are calculated using the worst-case PCI clock period of 30 ns. 70 x TPCI is 2.10 s for a 331/3 MHz clock.
5.2.
EEPROM Data Format
The contents of the EEPROM are used to generate a series of internal register writes in the OX16PCI958 - the data specifies a sequence of addresses to be written to and the byte to be written. Table 30 shows how the data in the EEPROM is organized. Table 30 EEPROM Data Organization
Address 00h 01h 02h ... end address Bits 15:8 of data sync. byte: must be 10h internal address internal address ... internal address Bits 7:0 of data end address in EEPROM data to write data to write ... data to write
After reset, the block reads the first word in the EEPROM. This word must contain the binary pattern 00010000 in its top 8 bits. The block uses this fact to work out the number of address bits required by the EEPROM in the following reads, thus allowing a wide range of EEPROM devices to be used. Now that the number of EEPROM address bits is known, the block knows where the data begins within the serial stream, and it reads the first EEPROM word again. It latches the bottom 8 bits of this word internally, and this value is used as the end-address of the data in the EEPROM. In the next phase, the block reads word 1 through to end-address in sequence, stopping after it has read the end-address word. It considers the top 8 bits of each word as an internal address and the bottom 8 bits as data. The block performs a write on its internal bus interface, using the address and data from the EEPROM word.
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5.3.
Example EEPROM Data
This section explains how to determine what EEPROM data must be written to the device and gives a worked example. To decide on the EEPROM data, first list the sequence of values that need to be written to registers and then work out the internal address for each register. Using the information in Table 30, EEPROM information is as follows: * * The first word (address 00h) in the EEPROM must have an upper byte of 10h, and a lower byte containing the value number of register writes. Following words must have an upper byte of internal address and a lower byte of data to write. For example, to configure a product with eight serial ports, the following configuration is required: * * * * * Set the PCI Vendor IDs to 1415h, and the Device IDs to 9538h Enable UARTs 0 to 7 Set the clock prescaler for UART 0 to 1Ch to divide clock by 3.5 (this is just to demonstrate a complex EEPROM sequence) Set the PCI ID codes by writing registers in the internal address range 00h-19h (see Table 12 on page 15). Set the UART enable and bank switching registers at internal addresses 40h, 41h and 4Ch, as described in section 3.2.
Setting the clock prescaler requires a sequence of writes, because the CPR is an indexed register. This type of setting is usually done by the device driver controlling the card, but the operation is included here as an example of how to do such a configuration, perhaps for use with an old device driver. In this worst-case example, it takes seven EEPROM words to change one UART register, but to add more register changes would not need so much EEPROM space. Before accessing an indexed register, the indexed register safety catch must be switched off, using the following sequence: 1. Switch off the safety catch for UART 0 2. Set IRSR for UART 0 to 16 (the index of the CPR) 3. Write the CPR value 4. Set IRSR for UART 0 back to 0, so that the scratch register is seen at offset 7 by default, for backwards compatibility 5. Switch the safety catch for UART 0 back on Table 31 shows how the example information above translates to EEPROM data.
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Table 31 Example EEPROM Data
Address in EEPROM 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Dh 0Eh 0Fh 10h 11h Bits 15:8 of EEPROM data: internal address 10h 00h 01h 08h 09h 02h 03h 0Ah 0Bh 40h C1h 86h 87h 86h C1h Bits 7:0 of EEPROM data: write data 12h 15h 14h 15h 14h 38h 95h 08h 95h FFh 00h 10h 1Ch 00h 80h Notes sync. byte and end address VID lower byte VID upper byte SVID lower byte SVID upper byte DID lower byte DID upper byte SDID lower byte SDID upper byte Enable UARTs 0-8 safety catch off for UART 0 set IRSR=16 set CPR=1Ch set IRSR=0 safety catch on
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6. CLOCK/OSCILLATOR PINS
The OX16PCI958 provides a clock input and a logically inverted output suitable for driving a crystal oscillator as shown below: Figure 5 OX16PCI958 Clock Provisions
VDD XTALI C1
R1
Crystal
R2 C2 XTALO
Oscillator clock to baud generator logic
Alternatively, the XTALI pin may be driven from an external clock signal, and the XTALO pin used as an optional clock output. Figure 6 OX16PCI958 Using External Clock Input
VDD External clock XTALI
Optional clock output
XTALO
Oscillator clock to baud generator logic
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7. OPERATING CONDITIONS
Table 32 Absolute Maximum Ratings
Min DC Supply voltage Input voltage Input current Storage temperature -55 -0.3 Max 7.0 VDD + 0.3 10 150 Unit V V A C
7.1.
Recommended Operating Conditions
Min Max 5.5 5.5 70 150 0 14.7 331/3 16 Unit V V C C MHz MHz 4.5 3.0 0
Supply voltage, VDD Supply voltage, VDDP Operating free-air temperature, TA Junction temperature, TJ Clock frequency (PCI clock, 'CLK') Oscillator/clock frequency (UART clock, 'XTALI')
7.2.
DC Characteristics
Table 33 CMOS Type Input, Supply at +5V 10%
Parameter Input low voltage, VIL Input high voltage, VIH Input leakage (no pull-up)
Min 0.7 x VDD -10
Max 0.3 x VDD 10
Unit V V A
Table 34 TTL Type Input, Supply at +5V 10%
Parameter Input low voltage, VIL Input high voltage, VIH Input leakage (no pull-up) 2.0 -10 10 Min Max 0.8 Unit V V A
Table 35 CMOS or TTL Type Output, Supply at +5V 10%
Parameter Output low voltage, VOL (sinking rated current) Output high voltage, VOH (sourcing rated current) 3-state output leakage current, IOZ -10 Min 2.4 0.4 10 Max Unit V V A
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8. I/O ELECTRICAL & TIMING SPECIFICATIONS
The host interface timings comply with all requirements of PCI specifications. In
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Table 36, the columns have the following meanings: I, O or B I--input O--output B--bi-directional I/O Output drive strength in mA
OX16PCI958 DATA SHEET
Drv Str CMOS / TTL CTO Ext Load ITC PU/PD Special
Type of voltage thresholds used; see details in the following section Clock-to-output timings, in ns. If only one number is given, this is the maximum External load (in pF) used to verify output timings Input-to-clock timings, in ns, i.e. setup time Indicates whether internal pull-up or pull-down resistors are fitted. All pull-ups have a 100 k nominal resistance, although they are not strictly ohmic in nature Particular I/O specifications, as follows: PCI Universal-- I/O conforms to the PCI 5V signaling specification when the VDDP pins are at 5V, and conforms to the PCI 3.3V signalling specification when the VDDP pins are at 3.3V. IEEE 1284 level 2-- I/O conforms to the "level 2" signalling specification defined in IEEE 1284-2000, when fitted with an external 22 series resistor (all signals) and 1.2 k pull-up resistors (input and bi-directional pins) Power/power voltage-- power or I/O pin is connected to the 3.3/5V I/O group used for the PCI interface, or the 5V group used for the other I/Os
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Table 36 Pin Electrical & Timing Characteristics
Pin Pin Name No. 1 2 3 4 5 6 7 8 9 AD23 VDDP AD22 AD21 AD20 VSS AD19 AD18 AD17 B B B B I I I O O O O O B I B B B B B B B B I B B B B B B CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS 2-11 2-11 2-11 2-11 2-11 2-11 2-11 2-11 2-11 2-11 2-11 2-11 2-11 2-11 2-11 2-11 2-11 2-11 2-11 2-11 2-11 2-11 2-11 2-11 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 Page 39 B B B CMOS CMOS CMOS 2-11 2-11 2-11 7 7 7 PCI Universal PCI Universal PCI Universal Drv Ext I, O CMOS / CTO / ITC / Str (in Load / PU/PD Special or B TTL ns ns mA) pF B CMOS 2-11 7 PCI Universal Signalling/ power voltage (in V) 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5
10 AD16 11 VDDP 12 C/BE#2 13 FRAME# 14 IRDY# 15 VSS 16 TRDY# 17 DEVSEL# 18 STOP# 19 PERR# 20 VDDP 21 SERR# 22 PAR 23 C/BE#1 24 VSS 25 AD15 26 AD14 27 AD13 28 AD12 29 VDDP 30 AD11 31 AD10 32 AD9 33 VSS 34 AD8 35 C/BE#0 36 AD7 37 AD6 38 VDDP 39 AD5 40 AD4 41 AD3 42 VSS 43 AD2 DS-0022 Nov 05
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Signalling/ power voltage (in V) 3.3/5 3.3/5 3.3/5 3.3/5
Pin Pin Name No. 44 AD1 45 AD0 46 VDD 47 VDDP 48 TESTN 49 VSS 50 EEDIO 51 VSS 52 EECK 53 EECS 54 RI7 55 DTR7 56 VDD 57 CTS7 58 SOUT7 59 RTS7 60 VSS 61 SIN7 62 DSR7 63 DCD7 64 RI6 65 VDD 66 DTR6 67 CTS6 68 SOUT6 69 VSS 70 RTS6 71 SIN6 72 DSR6 73 DCD6 74 VDD 75 RI5 76 DTR5 77 VSS 78 XTALI 79 XTALO 80 CTS5 81 NC 82 SOUT5 83 RTS5 84 VDD 85 SIN5 86 DSR5 87 DCD5 88 VSS DS-0022 Nov 05
Ext Drv ITC / CMOS / CTO / I, O PU/PD Special Load / Str (in ns TTL ns or B pF mA) B B CMOS CMOS 2-11 2-11 7 7 PCI Universal PCI Universal
I I B O O B O I O O I I B B O I O O I I B B O I O I O O I I B
-
CMOS CMOS CMOS CMOS CMOS
-
12 7 7
PU 20 PU PU PU PU PU PU PU PU PU PU PU -
global tri-state control Tie to GND
5 5 5 5 5
14 2 14 14 14 14 2 14 14 14 14 2
TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL * *
36 36 36 36 36 36 36 36 36 36 36 36 17 17 17 17 17 17 17
IEEE 1284 level 2
5 5 5 5
20 20 20 20 20 20 20 20 20 20 -
IEEE 1284 level 2 IEEE 1284 level 2
5 5 5 5
IEEE 1284 level 2 IEEE 1284 level 2
5 5 5 5
IEEE 1284 level 2 IEEE 1284 level 2 IEEE 1284 level 2
5 5 5 5 5
IEEE 1284 level 2 IEEE 1284 level 2
5 5 5 5
Crystal oscillator output Crystal oscillator input 36 36 36 17 17 20 20 20 20 PU PU PU PU IEEE 1284 level 2 IEEE 1284 level 2
5 5 5 5 5 5 5 5 5
2 2 14
TTL TTL TTL TTL TTL TTL
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Signalling/ power voltage (in V) 5 5 IEEE 1284 level 2 5 5 5 5 IEEE 1284 level 2 IEEE 1284 level 2 IEEE 1284 level 2 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Page 41
Pin Pin Name No. 89 RI4 90 DTR4 91 CTS4 92 SOUT4 93 VDD 94 RTS4 95 SIN4 96 DSR4 97 VSS 98 DCD4 99 DCD0 100 DSR0 101 SIN0 102 VDD 103 RTS0 104 SOUT0 105 CTS0 106 VSS 107 DTR0 108 RI0 109 DCD1 110 DSR1 111 VDD 112 SIN1 113 RTS1 114 SOUT1 115 VSS 116 CTS1 117 DTR1 118 RI1 119 DCD2 120 VDD 121 DSR2 122 SIN2 123 RTS2 124 VSS 125 SOUT2 126 CTS2 127 DTR2 128 RI2 129 VDD 130 DCD3 131 DSR3 132 SIN3 133 RTS3 DS-0022 Nov 05
Ext Drv ITC / CMOS / CTO / I, O PU/PD Special Load / Str (in ns TTL ns or B pF mA) B O I O O I I B I I I O O I O I I I I O O I O I I I I O O I O I I I I O 14 2 2 2 14 2 2 2 2 2 2 2 2 2 2 TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 17 17 17 17 17 17 17 17 17 17 17 17 17 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU IEEE 1284 level 2
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Signalling/ power voltage (in V) 5 5 5 5 5 5 3.3/5
Pin Pin Name No. 134 VSS 135 SOUT3 136 CTS3 137 DTR3 138 VDD 139 RI3 141 VDD 142 VSS 143 INTA# 144 RST# 145 CLK 146 PME# 147 VDDP 148 AD31 149 AD30 150 AD29 151 VSS 152 AD28 153 AD27 154 AD26 155 AD25 156 VDDP 157 AD24 158 VSS 159 C/BE#3 160 IDSEL
Ext Drv ITC / CMOS / CTO / I, O PU/PD Special Load / Str (in ns TTL ns or B pF mA)
O I O I
2 2 6
TTL TTL TTL TTL CMOS
36 36 36
17 17
20 20
PU PU -
140 LINEDRIVER_EN O
17
-
O I I O B B B B B B B B I I -
CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS 2-11 2-11 2-11 2-11 2-11 2-11 2-11 2-11 -
7 7 7 7 7 7 7 7 7 7 7
-
PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal PCI Universal
3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5
Note: Although the PME# pin is an open-collector output, it is not suitable for direct connection to the PCI bus. The PME# pin must be isolated from the host system when the OX16PCI958 power source is absent, so that it does not cause unwanted wake events. See section 7 of the PCI Bus Power Management Interface Specification, revision 1.1, for guidance on implementing the isolation.
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9. PACKAGE INFORMATION
The package is a standard 160-pin QFP package (JEDEC ref MS-022) with 0.65 mm lead pitch and a 4.1 mm max height from PCB, as shown in Figure 7. Figure 7 OX16PCI958 Package
D D1
PIN 1
E1
E
f
J C L e
A1
A
Lead coplanarity
Max 4.10 3.60 Basic Unit mm mm mm mm mm mm mm mm mm mm mm mm
Min A A1 C D D1 E E1 J L e f Lead coplanarity 3.20
0.23 31.20 28.00 31.20 28.00 0.25 0.73 0.22 0.50 1.03 0.65 0.40 0.10
Plastic body dimensions do not include flash or protrusion, max allowable 0.25 mm per side.
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10. GLOSSARY
BSC Basic spacing between centres QFP Quad Flat Pack RFU Reserved for future use: register bits described as RFU should be cleared during writes, and ignored during reads. They will be clear when read, but for future compatibility this should not be assumed. RO Read-only
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11. ORDERING INFORMATION
OX16PCI958-PQAG
RoHS compliant Revision Package Type - 160 QFP
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12. CONTACT DETAILS
Oxford Semiconductor Ltd. 25 Milton Park Abingdon Oxfordshire OX14 4SH United Kingdom
Telephone: Fax: Sales e-mail: Tech support e-mail: Web site:
+44 (0)1235 824900 +44 (0)1235 821141 sales@oxsemi.com support@oxsemi.com http://www.oxsemi.com
DS-0022 Nov 05
External--Free Release
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